The present invention relates to an IC testing apparatus in which a testing signal is inputted into a semiconductor device so that processing is carried out by the semiconductor device and the quality of the semiconductor device is judged by the result of processing. Also, the present invention relates to an IC testing method.
Conventionally, there is provided an IC testing apparatus for testing a semiconductor device having a correction circuit by which the wave-form of a signal inputted into the device to be tested is shaped and timing of the signal is corrected. Referring to FIGS. 4 to 6, the conventional IC testing apparatus having the correction circuit will be explained below.
FIG. 4 is an overall arrangement view showing an IC testing apparatus 100 which is an example of the conventional IC testing apparatus.
As shown in FIG. 4, the IC testing apparatus 100 includes: a pattern generator 2 for outputting a pattern signal 2a to test a device 3 to be tested; a circuit 20 for generating a testing signal 20a according to the pattern signal 2a outputted from the pattern generator 2; an analog comparator 4 for comparing an output signal 3a, which has been obtained by the operation of the device 3 to be tested according to the testing signal 20a, with a reference voltage inputted from the outside; a digital comparator 5 for comparing a result of the comparison conducted by the analog comparator 4 with an expecting pattern which is an expecting result of the test; and a timing generator 6 for generating a timing signal to control the operation of the digital comparator 5.
In this connection, in the device 3 to be tested of this IC testing apparatus 100, the testing signal 20a is inputted into a predetermined pin, and the output signal 3a is outputted from the same pin. While the device 3 to be tested is being tested, a state in which the testing signal 20a is inputted into the device 3 to be tested and written in the device 3 is defined as xe2x80x9cWrite Modexe2x80x9d, and a state in which the output signal 3a is read out from the device 3 to be tested and outputted from the device 3 is defined as xe2x80x9cRead Modexe2x80x9d.
The change-over between Write Mode and Read Mode is conducted by Write/Read change-over signal 2b outputted from the pattern generator 2.
While Write/Read change-over signal 2b is showing Write Mode, the test pattern is outputted from the pattern generator 2 as the pattern signal 2a, and the circuit 20 creates the testing signal 20a according to this pattern signal 2a. This testing signal 20a is inputted into the device 3 to be tested, and the device 3 to be tested carries out a predetermined processing according to the testing signal 20a. 
After the device 3 to be tested has carried out the predetermined processing according to the testing signal 20a, Write/Read change-over signal 2b is changed over to Read Mode.
While Write/Read change-over signal 2b is showing Read Mode, an expecting pattern to expect the result of processing of the device 3 to be tested is outputted as the pattern signal 2a and inputted into the digital comparator 5. The output signal 3a is outputted from the device 3 to be tested into the analog comparator 4.
On the other hand, a reference voltage of xe2x80x9cHixe2x80x9d level is inputted into VOH input terminal 41 of the analog comparator 4, and a reference voltage of xe2x80x9cLoxe2x80x9d level is inputted into VOL input terminal 42 of the analog comparator 4. The analog comparator 4 compares the signal level of the output signal 3a, which has been inputted from the device 3 to be tested, with the reference voltages of xe2x80x9cHixe2x80x9d and xe2x80x9cLoxe2x80x9d levels.
The digital comparator 5 operates according to the timing signal generated by the timing generator 6 and compares the signal inputted from the analog comparator 4 with the expecting pattern inputted as the pattern signal 2a, so that the digital comparator 5 judges the quality of the device 3 to be tested.
Further, IC testing apparatus 100 includes TG/FC circuit 21, which is arranged in the circuit 20. TG/FC circuit 21 generates a timing signal by a predetermined period and shapes a wave-form of the pattern signal 2a according to this timing signal. A signal outputted from TG/FC circuit 21 is subjected to timing correction by the timing correcting circuit 23.
The circuit 20 also includes TG/FC circuit 22 and the timing correcting circuit 24. These TG/FC circuit 22 and timing correcting circuit 24 conduct shaping the wave-form of Write/Read change-over signal 2b and correcting the timing.
Signals subjected to timing correction by the timing correcting circuits 23, 24 are inputted into the driver 25.
Signals are inputted from the timing correcting circuits 23, 24 into the driver 25, and further reference voltages are inputted into VIH input terminal 26 and VIL input terminal 29 of the driver 25. DENH signal 27a and DENL signal 28a are respectively inputted into DENH signal input terminal 27 and DENL signal input terminal 28.
In this case, DENH signal 27a is a signal for setting so that the signal level of the testing signal 20a can be xe2x80x9cHixe2x80x9d level when the device 3 to be tested is in Read Mode.
DENL signal 28a is a signal for setting so that the signal level of the testing signal 20a can be xe2x80x9cLoxe2x80x9d level when the device 3 to be tested is in Read Mode. In this connection when both DENH signal 27a and DENL signal 28a are at xe2x80x9cLoxe2x80x9d level, the signal level of the testing signal 20a is in a state of high impedance.
FIGS. 5A to 5D are timing chart showing a state of each signal in the test of the device 3 to be tested. In FIGS. 5A to 5D, FIG. 5A shows a pattern signal 2a, FIG. 5B shows a Write/Read change-over signal 2b, FIG. 5C shows DENH signal 27a and DENL signal 28a, and FIG. 5D shows a testing signal 20a. In this connection, xe2x80x9cHixe2x80x9d in the chart shows that the signal level of the testing signal 20a is at xe2x80x9cHixe2x80x9d level, xe2x80x9cLoxe2x80x9d in the chart shows that the signal level of the testing signal 20a is at xe2x80x9cLoxe2x80x9d level, and xe2x80x9cHiZxe2x80x9d in the chart shows a state of high impedance.
When the test of the device 3 to be tested is started at time t1, the pattern generator 2 outputs a signal showing Write Mode as Write/Read change-over signal 2b and also outputs a test pattern as the pattern signal 2a. Accordingly, the test pattern is inputted into the device 3 to tested as the testing signal 20a. In this connection, although both DENH signal 27a and DENL signal 28a are at the level of xe2x80x9cLoxe2x80x9d at this time, the testing signal 20a is not affected since Write/Read change-over signal 2b shows Write Mode.
When Write/Read change-over signal 2b is changed over to a signal showing Read Mode at time t2, an expecting pattern is outputted as the pattern signal 2a. In this connection, when both DENH signal 27a and DENL signal 28aare at the level of xe2x80x9cLoxe2x80x9d at this time, the testing signal 20a is in a state of high impedance xe2x80x9cHizxe2x80x9d.
When Write/Read change-over signal 2b is changed over to a signal showing Write Mode at time t3, a test pattern is outputted as the pattern signal 2a until time t4. In this period from time t3 to time t4, the state of each signal is the same as that in the period from time t1 to time t2.
In the successive period from time t4 to time t5, Write/Read change-over signal 2b shows Read Mode. Therefore, the expecting pattern is outputted as the pattern signal 2a. When one of DENH signal 27a and DENL signal 28a is at xe2x80x9cHixe2x80x9d level, the signal level of the testing signal 20a becomes a signal level corresponding to xe2x80x9cHixe2x80x9d level signal in DENH signal 27a and DENL signal 28a. 
FIG. 6 is a view showing a relation between the state of each signal and the operation of the driver 25 in IC testing apparatus 100.
As shown in FIG. 6, the pattern of the testing signal 20a agrees with the pattern of the pattern signal 2a when Write/Read change-over signal 2b shows Write Mode. When Write/Read change-over signal 2b shows Read Mode, as long as both DENH signal 27a and DENL signal 28a are at xe2x80x9cLoxe2x80x9d level, the testing signal 20a is in a state of high impedance. As long as one of DENH signal 27a and DENL signal 28a is at xe2x80x9cHixe2x80x9d level, the signal level of the testing signal 20abecomes a level indicated by DENH signal 27a and DENL signal 28a. 
That is, in Write Mode, the signal obtained when the pattern signal 2a is corrected by the circuit 20 is outputted as the testing signal 20a. In Read Mode, the signal level of the testing signal 20a becomes a state of xe2x80x9cLoxe2x80x9d level, xe2x80x9cHixe2x80x9d level or high impedance according to the state of DENH signal 27a or DENL signal 28a. 
In the aforementioned conventional IC testing apparatus 100, the wave-form of the pattern signal 2a and that of Write/Read change-over signal 2b are respectively shaped by TG/FC circuits 21, 22, and timing of the pattern signal 2aand that of Write/Read change-over signal 2b are respectively corrected-by the timing correcting circuits 23, 24.
Therefore, it is necessary to match timing in a plurality of systems. However, since there are provided two circuits of TG/FC circuits 21, 22 and also there are provided two circuits of the timing correcting circuits 23, 24, it becomes complicated to adjust timing. Therefore, it is difficult to enhance the accuracy of timing of each signal.
Depending upon the content of the test of the device 3 to be tested, terminals of IC testing apparatus 100 are respectively connected with a plurality of pins of the device 3 to be tested so as to conduct the test. In this case, the circuit structure of IC testing apparatus 100 becomes complicated. Accordingly, the size of the entire testing apparatus for testing the device 3 to be tested is increased, and the efficiency is lowered and the equipment cost is increased.
The present invention has been accomplished to solve the above problems. It is an object of the present invention to conduct shaping a wave-form of a signal inputted into a device to be tested and also conduct correcting timing of the signal, by a simple circuit structure with high accuracy.
In order to solve the above problems, the invention described in aspect 1 provides an IC testing apparatus for testing a device to be tested in such a manner that a predetermined testing signal is inputted into the device to be tested so that processing is carried out according to the testing signal, comprising:
a signal output means for outputting a signal after the change-over between the testing signal and a predetermined logical level signal (for example, a logic circuit 11);
a wave-form shaping means for shaping a waveform of the signal outputted from the signal output means (for example, TG/FC circuit 12);
a correcting means for correcting an output time of the signal, the wave-form of which is shaped by the wave-form shaping means (for example, a timing correcting circuit 13);
an amplifying means for amplifying a signal outputted from the correcting means to a predetermined logical level and outputting it to the device to be tested (for example, a driver 14); and
a judging means for judging the quality of the device to be tested according to the result of processing conducted in the device to be tested when the testing signal is inputted from the amplifying means into the testing device (for example, an analog comparator 4 and digital comparator 5).
According to the invention described in aspect 1, in an IC testing apparatus for testing a device to be tested in such a manner that a predetermined testing signal is inputted into the device to be tested so that processing is carried out according to the testing signal, the change-over between the testing signal and a predetermined logical level signal is conducted by the signal output means and the testing signal or the predetermined logical level signal, which has been changed over in this way, is outputted, the wave-form of a signal outputted from the signal output means is shaped by the wave-form shaping means, the output timing is corrected by the correcting means and the thus corrected timing is outputted, the signal outputted from the correcting means is amplified to a predetermined logical level by the amplifying means, the thus amplified signal is outputted to the device to be tested, and the quality of the device to be tested is judged by the judging means according to the result of processing of the device to be tested after processing has been conducted on the device according to the testing signal outputted from the amplifying means.
The invention described in aspect 5 provides an IC testing method in which a predetermined testing signal is inputted into a device to be tested and processing is carried out according to the testing signal so as to test the device to be tested, comprising the processes of:
a first process in which a signal is changed over between the testing signal and the predetermined logical level signal and outputted (for example, a process of the logical circuit 11);
a second process in which a wave-form of the signal outputted from the first process is shaped and the signal is outputted after the timing of output has been corrected (for example, a process of TG/FC circuit 12 and the timing correcting circuit 13);
a third process in which the signal outputted from the second process is amplified to a predetermined logical level and outputted to the device to be tested (for example, a process of the driver 14), and
a fourth process in which the quality of the device to be tested is judged by the result of processing of the device to be tested according to the testing signal outputted from the third process (for example, a process of the analog comparator 4 and the digital comparator 5).
Accordingly, in the test in which the testing signal is inputted into the device to be tested and the device is made to conduct processing according to this testing signal so that the quality of the device to be tested can be judged according to the result of processing, while the result of processing is being outputted from the device to be tested, the signal of a predetermined logical level can be outputted to the device to be tested.
According to the present invention, the testing signal is inputted into the device to be tested, and at the same time, the signal of a predetermined logical level can be easily outputted to the device to be tested. Further, the testing signal or the signal of the predetermined logical level can be outputted after the change-over has been conducted between the testing signal and the signal of the predetermined logical level. Therefore, a series of circuits, in which the signal is amplified after the waveform form of the outputted signal has been shaped and timing has been corrected, can be realized by a simple circuit structure. Accordingly, the size of the entire IC testing apparatus can be reduced, and further the accuracy of timing correction can be enhanced.
The invention described in aspect 2 provides an IC testing apparatus according to aspect 1, further comprising a mode designating means (for example, a pattern generator 2) for designating a mode obtained after the change-over between an input mode in which the testing signal is inputted into the device to be tested and an output mode in which the result of processing is outputted from the device to be tested, wherein the signal output means outputs a signal obtained after the change-over between the testing signal and the predetermined logical level signal according to the mode designated by the mode designating means.
According to the invention described in aspect 2, the mode designating means changes over and designates between the input mode in which a testing signal is inputted into the device to be tested and the output mode in which the result of processing is outputted from the device to be tested in the IC testing apparatus described in aspect 1, and the signal output means changes over and outputs between a testing signal and a predetermined logical level signal according to the mode designated by the mode designating means.
Accordingly, since the signal change-over means changes over a signal outputted according to the designation conducted by the mode designating means, the signal can be easily changed over at more accurate timing.
The invention described in aspect 3 provides an IC testing apparatus according to aspect 2, in which the mode designating means changes over a signal between the signal for designating the input mode and the signal for designating the output mode, and the signal output means outputs the testing signal while the mode designating means is outputting a signal to designate the input mode and the signal output means outputs the predetermined logical level signal while the mode designating means is outputting a signal to designate the output mode.
According to the invention described in aspect 3, in the IC testing apparatus described in aspect 2, the mode designating means changes over and outputs between a signal to designate the input mode and a signal to designate the output mode, and the signal output means outputs a testing signal while a signal to designate the input mode by the mode designating means is being outputted, and the signal output means outputs a predetermined logical level signal while a signal to designate the output mode is being outputted.
Accordingly, while a signal to designate the input mode is being outputted by the mode designating means, a testing signal is outputted, and while a signal to designate the output mode is being outputted, a predetermined logical level signal is outputted. Therefore, the signal can be changed over by the signal change-over means when a plurality of signals are combined with each other. Accordingly, the signal change-over means can be composed of a simple logical circuit. Due to the foregoing, the size of the entire IC testing apparatus can be more decreased and further the equipment cost can be reduced. Furthermore, the accuracy of timing can be more enhanced.
The invention described in aspect 4 provides an IC testing apparatus according to aspect 1, 2 or 3, further comprising an expecting processing result output means (for example, a pattern generator 2) for outputting an expecting processing result which is a processing result in the case where the quality of the device to be tested is high, wherein the quality of the device to be tested is judged by comparing the expecting processing result outputted from the expecting processing result output means with the processing result outputted from the device to be tested.
According to the invention described in aspect 4, in the IC testing apparatus described in one of aspects 1 to 3, the expecting processing result output means outputs an expecting processing result which is a processing result in the case where the quality of the device to be tested is high, and the judging means compares the expecting processing result outputted from the expecting processing result output means with the processing result outputted from the device to be tested, so that the quality of the device to be tested can be judged.
Accordingly, the quality of the device to be tested can be easily judged when the expecting processing result and the result of processing actually outputted from the device to be tested are compared with each other. Therefore, it is possible to realize an IC testing apparatus, the circuit structure of which is simple, capable of judging the quality of a device to be tested at low equipment cost.